Nick Tredennick
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Nick Tredennick is an IEEE fellow and a prominent American manager, inventor and VLSI design engineer. In 1968 he obtained the BSEE degree, and in 1970 the MSEE at Texas Tech University, Lubbock, TX, and, in 1976 the Ph.D. at Electrical Engineering, University of Texas, Austin, TX. From 1977 to 1979 Nick Tredennick was a Senior Design Engineer at Motorola, where he developed the logic and microcode for the Motorola 68000 microprocessor: the first commercialized product obtained by the structured VLSI design methodology, which demonstrated the supremacy of this methodology over a concurrently done "spaghetti structure" 8080-type design example by halving the design time as well as the debugging time. From 1979 to 1987 he worked as a research staff member and a project manager for the IBM T.J. Watson Research Center, Yorktown Heights, NY, where he did the microcode and logic design for the Micro/370 microprocessor (about 200,000 transistors) and wrote a book, Microprocessor Logic Design, published in 1987. From 198 to 1984, on sabbatical leave from IBM, he joined the Visiting Faculty, EECS, University of California, Berkeley, CA, to teach computer organization, chip design, and the Flowchart Method to upper division and graduate students.
From 1987 to 1988, when he was Director of Product Development, Nexgen Microsystems, San Jose, CA, he built and managed Nexgen’s engineering organization. He was a founder of the company, which went public in May 1995 and later merged into AMD. In 1988 he founded his own Tredennick, Inc., San Jose, CA, consulting on custom and semi-custom VLSI CPU design and reconfigurable computing, and, analyzing microprocessor industry trends. From 1993 to 1995 he has been Chief Scientist of Altera Corporation, San Jose, CA. 2000 he joined Gilder Publishing, Great Barrington, MA as an editor of the Gilder Technology Report on leading-edge components and to speak on topics in semiconductors, dynamic logic, and MEMS (microelectromechanical systems).
Nick Tredennick has been the first expert, recognizing and announcing Reconfigurable Computing as an essential paradigm shift in computer science, leading to the decline of the dominance of the classical instruction-stream-based computing. He has been often invited as a panelist and as a keynote speaker to international conferences, where he addressed future trends in the race beween microprocessor and Reconfigurable Computing and pointed to marketing opportunities missed by FPGA vendors.
[edit] Other Activities
- Registered Professional Engineer (Texas #44328). Commercial multi-engine instrument pilot’s license. CA commercial driver.
- Army Science Board (1994-2001 reports to Secretary of the Army). Texas Tech Electrical Engineering Academy (Elected 1994).
- Texas Tech Distinguished Engineering Graduate (Elected 1997). Nine patents in microprocessor implementation and computing.
- IEEE Fellow
- IEEE Accreditation Board for Engineering and Technology (ABET) reviewer for EE and for CE (1982-1986, 1991- ).
- IEEE-ABET Committee on Engineering Accreditation Activities (CEAA) (1994- ).
- IEEE representative to the Engineering Accreditation Commission (EAC) (2000- ); member, Executive Committee.
- Contributing Editor Microprocessor Report. Editorial Advisory Board for Microprocessors and Microsystems, for Embedded Developers Journal, and for IEEE Spectrum.
- USAF Undergraduate Pilot Training, Laredo AFB, TX, 1970-1971. Academic Training Award (top academic student).
- Major and Senior Pilot, U.S. Air Force (active, reserve, and National Guard; 1970-1984).
- Captain and Aerospace Engineering Duty Officer, U.S. Naval Reserve (1986-2000), retired.
[edit] Literature
- N. Tredennick:Microprocessor-based Computers; Computer, Vol. 29 No. 10, October 1996, pp. 27-37.
- N. Tredennick: Microprocessor Logic Design. Bedford, MA: Digital Press, 1987
- N. Tredennick: Implementation Decisions for the MC68000 Microprocessor, Proceedings of the 3rd Rocky Mountain Symposium on Microcomputers: Systems, Software, Architecture. August 1979
- N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 Aug 1996, pp 25-27.