Montecito (processor)
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- For other uses of "Montecito", see Montecito (disambiguation).
Montecito is the code-name of a major release of Intel's Itanium 2 Processor Family (IPF), which implements the IA-64 instruction set architecture on a dual-core processor. It was officially launched by Intel on July 18, 2006 as the "Dual-Core Intel Itanium 2 processor". According to Intel, Montecito doubles performance versus the previous, single-core Itanium 2 processor, and reduces power consumption by about 20%.[1] It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization.
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[edit] Architectural Features and Attributes
- Two cores per die
- 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, database-like workloads should improve by 15-35%.
- a total of 4 threads per die
- separate 16 KB Instruction L1 and 16 KB Data L1 cache per core
- separate 1 MB Instruction L2 and 256 KB Data L2 cache per core, improved hierarchy
- 12 MB L3 cache per core, 24 MB L3 per die
- 1.72 billion transistors per die, which is added up from:
- Die size is 27.72 mm x 21.5 mm, or 596 mm²
- 90 nanometer design
- Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count and higher clock speeds; 75-104 W. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistors were used, while high-speed, thus high-leakage ones where it was necessary.
- Demand Base Switching — power saving feature. Dynamically reduces processor power consumption based on demand or load. Works in conjunction with the OS. Could reduce server power consumption for typical CPU utilization.
- Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology.
- Virtualization technology allowing multiple OS instances per chip. This was known as Silvervale technology during development, and is now called Intel Virtualization Technology.
- Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. It is meant to be at system level (per node, with 4 dies). System throughput per node should be at least 21 GB/s, which suggest dual 333.333 MHz (double pumped, resulting 2x667 effective MHz) front side bus. However, it is up to system integrators how they organize their bus topology.
- All Montecito processors support 533MHz/400MHz FSB speed.
- Also available with legacy FSB for upgrading existing system designs.
- Eliminates the hardware-based x86 instruction emulation circuity, in favor of the more efficient software-based IA-32 Execution Layer"[2]
On October 25, 2005 it was officially announced by Intel that the first dual-core Itanium processor would be delayed until "the middle of next year." [3] Montecito was launched on July 18, 2006. Due to unspecified issues, Intel’s Foxton power management technology was disabled in the first release of Montecito, and the front-side bus frequency was reduced to 267MHz (533.333 MHz effective) instead of the 333MHz speed originally scheduled for the design [3]. In addition, higher binned parts will likely arrive later in 2006, or in 2007. This delay may be a result of the validation process of such a highly complex, high-end MPU. Unofficial insider sources previously told, and Intel papers confirmed, that Montecito is able to reach beyond 2.2 GHz with Foxton. The maximum Montecito's design is validated for is 2.5 GHz, but it's more likely that it will actually top out around 2.2 GHz in its lifecycle.
At the time of launch, the following models and pricing were available:
- Itanium 2 9050 1.60 GHz / 24 MB L3 -- $3,692
- Itanium 2 9040 1.60 GHz / 18 MB L3 -- $1,980
- Itanium 2 9030 1.60 GHz / 8 MB L3 -- $1,552
- Itanium 2 9020 1.42 GHz / 12 MB L3 -- $910
- Itanium 2 9015 1.40 GHz / 12 MB L3 -- $749
- Itanium 2 9010 1.60 GHz / 6 MB L3 / single core --$696
[edit] Successors
- Montvale
In contrast to earlier speculations, there will be no 65 nanometer shrink for this next-generation Itanium 2 processor, but the codename Montvale will cover a Montecito-on-steroids, released approximately one year later, at the tail end of 2006. Earlier data suggested that Montvale's clock speed would have likely hit 2.5-2.6 GHz, sitting on a 400 MHz FSB. As of today, Montvale might reach only 2 GHz, and considering Montecito's delay, it is possible that delivery could slip as well.
It is also very likely that, as with Montecito, Montvale will arrive along with updated Itanium compiler technology. This should provide additional improvements in the performance characteristics of Itanium servers.
- Tukwila
Montvale's successor is Tukwila, the first 65 nm design, due in 2008. Consisting of at least 4 cores, which will likely be microachitecturally the same as Montecito's, it should fit into the Common System Interface (CSI), which Itanium will share with Intel's Xeon family of server processors. CSI should make it easier for chip and server vendors to leverage their development efforts across both Itanium and Xeon server architectures. Additional major architectural advances are not expected till Poulson, about which very little is known at this time.
[edit] See also
[edit] External links
- DeMone, Paul (2004-10-04). Real World Technologies: Sizing up the Super Heavyweights. Real World Technologies. -- an analysis and comparison of Montecito and POWER5 with performance estimates
- Willard Ph.D., Christopher G.; Matthew Eastwood, Jie Wu, Addison Snell (July 2006). Intel Brings Dual-Core Capabilities to Itanium 2 with Montecito Processor. Manufacturing Insights.
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