Logic Optimization
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Logic Optimization a part of Logic Synthesis, is the process of finding an equivalent representation of the specificied Logic Circuit under one or more specified constraint. Generally the circuit is constrained to minimum chip area meeting a prespecified delay.
[edit] Introduction
With the advent of Logic Synthesis, one of the biggest challenge in front of EDA Industry was to find the best netlist representation of the given design description. While Two-Level Logic Optimization had long existed in the form of Quine–McCluskey algorithm, the rapidly improving chip densities, and the wide adoption of HDLs for circuit description, formalized the Logic Optimization domain as it exists today.
Today, Logic Optimization is divided into various categories based on two criteria:
Based on Circuit Representation
Two-Level Logic optimization Multi-Level Logic Optimization
Based on Circuit characteristics
Sequential Logic Optimization Combinational Logic Optimization
While Two-Level Circuit Representation of Circuit strictly refers to the flattened view of the circuit in terms of Sum-Of-Products (SOPs), more applicable to PLA implementation of design, Multi-Level Representation is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs(Product-Of-Sum), Factored form etc.
On the other hand, we distinguish between Sequential and Combinational circuits, whose behavior can be described in terms of Finite State Machine(FSM) state tables/diagrams or by Boolean Functions and relations respectively.
[edit] See also
[edit] References
- Synthesis and Optimization of Digital Circuits, by Giovanni De Micheli, ISBN 0-07-016333-2.
