Layout versus schematic

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Layout Vs. Schematic check (LVS) is the area of Electronic design automation software that determines whether a particular chip layout corresponds to the original schematic or circuit diagram of the design.

1 Background
2 LVS Check
3 LVS Software
4 Commercial LVS Software
5 External links

[edit] Background

A successful Design rule check ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where LVS comes into the picture.

[edit] LVS Check

LVS-check recognizes the electrical components of the layout, as well as the connections between them, and compares them with the schematic or circuit diagram.

LVS Checking involves following three steps:

Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. It then runs the database through many logic operations to determine the semiconductor components represented in the drawing by their layers of construction. It then examines the various drawn metal layers and finds how each of these components connects to others.
Reduction: During reduction the software generates a [netlist] representation of the layout database.
Comparison: The extracted layout netlist is then compared this to a netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be "LVS clean."