Intel P6

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The P6 microarchitecture is the sixth generation x86 microprocessor architecture of Intel, released in 1995. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M iteration of the P6 microarchitecture is the Intel Core microarchitecture iteration.

1 From Pentium Pro to Pentium III
2 Revived architecture in Pentium M (Banias and Dothan)
3 Intel Core (Yonah)
4 P6 based chips
5 See also

[edit] From Pentium Pro to Pentium III

The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was in the design of the Pentium Pro CPU in the mid-nineties, the immediate successor to the original Pentium design (P5).

Some techniques first used in the x86 space in the P6 core include:

Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
Integrated L2 cache that runs at the full speed of the processing core, instead of the earlier designs of off-die (on motherboard) cache, which runs at a fraction of the CPU frequency.
Wider 36-bit physical address bus to support more than 4 GiB of physical memory (the linear address space of a process was still limited to 4 GiB).
Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.

The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.

[edit] Revived architecture in Pentium M (Banias and Dothan)

However, it was soon realized that the new NetBurst core was not suitable for mobile computing which required a cool and efficient core, and sometimes the NetBurst Thermal Envelope reaches very high levels (such as 115W of the Prescott revisions); and hence an improved version of the P6 core was revived, and brought back in the form of the Pentium M family, with certain modifications:

Faster front side bus, which in Banias would equal the 400MHz Bus of the Pentium 4 A revision of the Northwood core CPUs, and raising to 533MHz with the introduction of Alviso chipset in early 2005.
Larger L2 cache, first 1MB, then 2MB in the Dothan, means great performance on single thread applications with datasets that do not come close to 2MB in size. Such as 1MB PI calculations.
SSE2 support.
Pipelining lengthening by 3-4 stages.
Dedicated register stack management.
Addition of global history to branch prediction table.
Fusion of certain sub-instructions mediated by decoding units.
Enhanced SpeedStep III (EIST).
Dynamic cache activation by quadrant selector from sleep states.

The Pentium M, as it exists in current form, has some major shortcomings:

Floating point unit (FPU) performance definitely falls short of the capabilities of other components, since only one FP unit is present in the P6 core, and does not have the double pumping benefit that the ALU possesses.
It has very limited system bandwidth, as compared to NetBurst and AMD64 (which contains 800-1000MHz HyperTransport, as well as independent memory channels); with total front side bus bandwidth of 400 (100 MHz quad-pumped) or 533 (133 MHz quad-pumped) MHz, barely allowing data from one channel of DDR-II 533 memory controller to transmit at once.
Suffers from memory latency problems due to memory controller being in the northbridge instead of on-die.
No SSE3 support, which means that some high-end multimedia applications won't run as efficiently.

[edit] Intel Core (Yonah)

Yonah, launched in January 2006 under the brand name Intel Core, with Intel Core Solo and Intel Core Duo for single and dual core derivatives respectively, provides partial solutions to some of these shortcomings, by adding to the Pentium M microarchitecture: