User:Henriok/PowerPC 600
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The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the 603, 604 and the 64-bit 620.
The real family is the 601, 603, 604 and 620. All others are either derivative work or completely different processors, sharing the name only as prototypes.
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[edit] Nuclear family
[edit] PowerPC 601
The PowerPC 601 was the first generation of microprocessors to support a subset of the PowerPC instruction set. It was introduced at the same time as IBM POWER2 line of processors. Basically it a simpified and thus cheaper version of the RISC Single Chip (RSC) processor, with support for some PowerPC instructions not in the POWER instruction set added. Worth noting is that it didn't include all the PowerPC instructions, so it acted more like a bridge between the POWER and the future PowerPC processors. It did also included the 60x bus technology from Motorolas 88110 RISC-processors. It was designed in just 12 months and was pushed hard to establish PowerPC on the market early.
The was designed to suit several applications and had support for external L2 cache and SMP. It had a four stage pipeline 4 functional units, including a floating point unit, an integer unit, a branch unit and a sequencer unit (a little used heritage from the RSC). The processor also included a memory management unit.
It was launched in 1993, manufactured by both IBM and Motorola, using a 0.6 µm aluminium based CMOS process, at speeds rannging from 50 to 80 MHz. The die was 121 mm² large, had 2.8 million transisors and included 32 kB unified L1 cache which was very much at the time. Thanks partly to the large cache it was considered a high performance processor in its segment, readily beating Intel's competitor Pentium. PowerPC 601 was used in the first Power Mac computers from Apple, and in some RS/6000 machines from IBM.
[edit] PowerPC 601v
An updated version, PowerPC 601v, 74 mm² small using a 0.5 µm fabrication process, followed in 1994 with speeds 100-120 MHz.
[edit] PowerPC 603
The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. It was designed to be a low cost, low end processor for portable and embedded use. One of the main fetures was power saving functions (doze, nap and sleep mode) that could reduce power dramaticly, drawing only 2 mW in sleep mode. The 603 have four stage pipline and five execution units; interget unit, floating point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8kB L1 caches for instructions and a 32/64 bit 60x memory bus, reaching up to 75 MHz. The 603 core doesn't support SMP in hardware.
The PowerPC 603 had 1.6 million transistors and was manufactured by IBM and Motorola on a 05 µm fabrication process. The die was 85 mm² large drawing 3W at 80 MHz. The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC "G3".
It was used in low end and portable Macintosh models but also found widespead use in different embedded appliances. The processor got a somewhat bad reputation in Apple's computers since the 68k emulation software didn't fit into the relatively small caches causing some degraded perfromance in older software.
[edit] PowerPC 603e / 603ev
The performance issues of the 603 was adressed in the PowerPC 603e. The L1 caches was enlarged and enhanced to 16 kB four-way set-associative data and instruction caches. The clockspeed of the processors was doubled too, reaching 200 MHz. Later on, while shrinking the fabrication process to 0.35 µm, speeds up to 300 MHz was achieved. This part is sometimes called PowerPC 603ev. The 603e and 603ev have 2.6 million transistors each and are 98 mm² and 78 mm² large respectively. The 603ev draws a maximum of 6 W at 300 MHz.
The PowerPC 603e was the first mainstream desktop processor to reach 300 MHz. The 603e was also used in accelerator cards from Phase5 for the Amiga line of computers, with CPUs ranging in speeds from 160 to 240 MHz. It was also the heart of the BeBox which sported two PowerPC 603 processors running at 66 or 133 MHz. The PowerPC 603e is still sold today by IBM and Freescale, and others like Atmel.
[edit] G2
The PowerPC 603e core, renamed G2 by Freescale, is the basis for many embedded PowerQUICC II processors, and as such it keeps on beeing developed. Freescale's PowerQUICC II SoC processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz.
[edit] e300
Freescale have enhanced the 603e core, calling it e300, in the PowerQUICC II Pro line embedded processors. The added larger 32/32 kB L1 caches and other performance enhancing measures. Freescale's PowerQUICC II Pro SoC processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz.
[edit] PowerPC 604
The PowerPC 604 was introduced in 1994 alongside the 603 and was designed as a hign performance chip for workstations and entry level servers and had as such support for symmetric multiprocessing in hardware. The 604 was used extensively in Apple's high end systems and was also used in in Macintosh clones, IBM's low end RS/6000 servers and workstations, accelerator bords to Amigas and as an embedded CPU for telecom applications.
The 604 is a superscalar processor capable of issuing four instructions simultaneously. The 604 has a six stage pipeline and six execution units that can work in parallel, finishing up to six instructions every cycle. Two simple and one complex integer units, one floating point unit, one branch processing unit managing out-of-order execution and one load/store unit. It has separare 16 kB data and instruction L1 caches and a 32/64 bit 60x memory bus, reaching up to 50 MHz.
The PowerPC 604 had 3.6 million transistors and was manufactured by IBM and Motorola on a 0.5 µm fabrication process. The die was 196 mm² large drawing 14-17W at 133 MHz. It operated at speeds between 100 and 180 MHz.
[edit] PowerPC 604e
The PowerPC 604e was introduced in 1996 and added a a condition register unit and separate 32 kB data and intruction L1 caches among other changes to its memory subsystem and branch predition unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35 µm fabrication process. The die was 148 mm² or 96 mm² large, manufactured by Motorola and IBM respectively, drawing 16-18W at 233 MHz. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.
[edit] PowerPC 604ev "Mach5"
The PowerPC 604ev, 604r or "Mach 5" was introduced in 1997 and was essentially 604e fabricated by IBM and Motorola on a newer process, reaching higher speeds and a lower energy consumption. The die was 47 mm² small manufactured on a 0.25 µm process drawing 6W at 250 MHz. It operated at speeds between 250 and 400 MHz and supported a memory bus up to 100 MHz.
When Apple dropped the 604ev in 1998, in favour for the PowerPC 750, IBM kept using it in low end RS/6000 computers for several years.
[edit] PowerPC 620
The PowerPC 620 was the first 64-bit processor implementing the entire PowerPC Architecture. It was a second generation PowerPC along side of 603 and 604, but geared towads the high end workstation and server market. It was powerful on paper and was initially supposed to be lanuched alongside its breathren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e beat it. The 620 was therefor never produced in large quantities and found very little use. The sole user of PowerPC 620 was Groupe Bull in its Escala UNIX machines, but they didn't deliver any large numbers. IBM who intended to use it in workstations and servers decided to wait for the even more powerful RS64 and POWER3 64-bit processors instead.
The 620 was similar to the 604. It has a five stage pipleine, same support for symmetric multiprocessing and the same number of excecution units; a load/store unit, a branch unit, an FPU, and three integer units. With a same larger 32/32 kB L1 cache, a wider and faster 128 bit memory bus, with access to up to 128 MB large L2 caches, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch prediction table was also larger and could discpatch more instruction so that the processor can handle out of order execution more efficiently than the 604. The floating point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instruction in hardware (like sqrt) made it, combined with faster and wider databuses, a more efficient than the FPU in 604.
The 620 was produced by Motorola in a 0.5 µm process, it had 6.9 million transistors, and the die was 311 mm² large. Speeds at 120-150 MHz, drawing 30 W at 133 MHz. A later model was built using a 0.35 µm, reaching 200 MHz.
- Article in BYTE
- Contribution to the history of Unix at Bull (Interessting reading concerning the use of PowerPC 620 at Bull. In French)
[edit] Extended family
[edit] PowerPC 602
The PowerPC 602 was a stripped down version of PowerPC 603, specially made for game consoles. It has reduced L1 caches (4k instruction and 4k data), a singe precision floating point unit and a back scaled branch prediction unit. It was offered at speed ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It comprised of 1 million transistors and it was 50 mm² large manufactured at a 0.5 µm process.
3DO developed the M2 game console with two PowerPC 602, but it was never marketed.
[edit] PowerPC 603Q
In 1996 the fabless semiconductor company Quantum Effect Devices (QED) made a PowerPC 603 compatible processor named "PowerPC 603Q" which didn't have anything, but the name, in common with any other 603. It was a from ground up implementation of the 32 bit PowerPC specification targeted at the high end embedded market. As such it was small, simple, energy effcient, but powerful; equaling the more expensive 603e while drawing less power. It hade an in order, 5 stage pipeline with a single integer unit, a double precision floating point unit and separate 16 kB instruction and 8 kB data caches. It was 69 mm² small using a 0.5 µm fabrication process and drew just 1.2 W at 120 MHz.
603Q was designed for Motorola, but they withdrew from the contract before 603Q went into full production and QED could not continue market the processor since they lacked a PowerPC license of their own.
[edit] PowerPC 613
"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC. It supposedly was renamed "PowerPC 750" in response to Exponential's x704 processor that was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculations, or a reference to a completely different processor.
[edit] PowerPC 614
Similar to PowerPC 613, the "PowerPC 614" might have been a name given by Motorola to a third generation PowerPC, and later renamed by the same reason as 613. It's been suggested that the part was renamed "PowerPC 7400", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculations, or a reference to a completely different processor.
[edit] PowerPC 615
The "PowerPC 615" is a little known PowerPC processor announced by IBM in 1994. Its main feature was to incorporate an x86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions. An operating system running on PowerPC 615 could either chose to execute 32 bit or 64 bit PowerPC instructions, 32 bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. Minix and a special developer version of OS/2 could run.
It was 330 mm² large (rather large) manufactured by IBM on a 0.35 µm process. It was pin compatible with Intel's Pentium processors and comparable in speed. The processor was only produced in prototype examples and the programme was killed in part by the fact that Microsoft would probably never give support for the processor. Engineers working on the PowerPC 615 would later find their way to Transmeta working on their Crusoe processor.
[edit] PowerPC 625
"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "RS64". The designation "PowerPC 625" was never used for the final processors.
[edit] PowerPC 630
"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the POWER and PowerPC instruction sets. It was later renamed "POWER3", probably to separate it from the more consumer oriented "PowerPC" processors used by Apple.
