Fanout

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Fanout is a measure of the ability of a logic gate output, implemented electronically, to drive a number of inputs of other logic gates of the same type. In most designs, logic gates are connected together to form more complex circuits, and it is common for one logic gate output to be connected to several logic gate inputs. The technology used to implement logic gates usually allows gate inputs to be wired directly together with no additional interfacing circuitry required.

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to drive any number of gate inputs. However, since real-world fabrication technologies exhibit less than perfect characteristics, in reality a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting to do so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.

The fanout is simply the number of inputs that can be connected to an output before the current required by the inputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. The current figures may be different for the logic zero and logic one states and in that case we must take the pair that give the lower fanout. This can be expressed mathematically as

Fanout = \operatorname{min}\left ( \left\lfloor\frac{I_{outhigh}}{I_{inhigh}}\right\rfloor ,\left\lfloor\frac{I_{outlow}}{I_{inlow}}\right\rfloor \right )

(\lfloor\;\rfloor is the floor function).

Going on these figures alone TTL logic gates are limited to perhaps 2 to 10, depending on the type of gate, while CMOS gates have fanouts that are generally far higher than is likely to occur in practical circuits (e.g. using NXP Semiconductor specifications for their HEF4000 series CMOS chips at 25°C and 15V gives a fanout of 34 thousand).

However inputs of real gates have capacitance as well as resistance to the power supply rails. This capacitance will slow the output transition of the previous gate and hence increase its propogation delay. As a result rather than a fixed fanout the designer is faced with a trade off between fanout and propagation delay (which affects the maximum speed of the overall system). This effect is less marked for TTL systems, which is one reason why they maintained a speed advantage over CMOS for many years.

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