Esterel Studio
From Wikipedia, the free encyclopedia
Esterel Studio is a design environment based on the Esterel language. It is optimized for hardware IPs (such as DMAs, protocols, cache controllers, I/O subsystems, etc.) dedicated at capturing formal design specifications, enabling formal verification of properties very early in the design phase, and automating the production of synthesizable RTL (VHDL and Verilog), both for prototyping and production purposes.
[edit] Features
- Rigorous executable specifications.
- Unlimited hierarchical design and synthesis flow.
- Support of signed / unsigned integers of arbitrary size or arithmetic with no bit loss.
- Generated VHDL, Verilog, C, C++, SystemC all share the same exact behavior.
- Powerful sequential control and preemption primitives.
- Co-simulation with all HDL simulators.
- Automatic detection of potential data overflow.
- Automatic VHDL and C testbench generation.
- Formal verification of properties and assertions.
- ECO support and critical path displays.
