DDR SDRAM
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| DRAM types |
DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on both the rising and falling edges of the clock signal (double pumped). This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation.
With data being transferred 8 bytes at a time DDR RAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 8 (number of bytes transferred). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s.
JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules.
As DDR is superseded by the newer DDR2, the older version is often now referred to as DDR1.
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[edit] Chip specification
- DDR-200: DDR-SDRAM memory chips specified to operate at 100 MHz
- DDR-266: DDR-SDRAM memory chips specified to operate at 133 MHz
- DDR-333: DDR-SDRAM memory chips specified to operate at 166 MHz
- DDR-400: DDR-SDRAM memory chips specified to operate at 200 MHz
[edit] Chip characteristics
- DRAM density. Size of the chip in megabits. Example: 256 Mbit — 32 megabyte chip.
- DRAM organization. Written in the form of 64M x 4, where 64M is a number of storage units (64 million), x4 (pronounced «by four») — number of bits per chip, which equals the number of bits per storage unit. There are x4 and x8 DDR chips. The former allows the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC, while the latter chips are somewhat cheaper.
[edit] Stick/module specification
- PC-1600: DDR-SDRAM memory module specified to operate at 100 MHz using DDR-200 chips, 1.600 GByte/s bandwidth
- PC-2100: DDR-SDRAM memory module specified to operate at 133 MHz using DDR-266 chips, 2.133 GByte/s bandwidth
- PC-2700: DDR-SDRAM memory module specified to operate at 166 MHz using DDR-333 chips, 2.667 GByte/s bandwidth
- PC-3200: DDR-SDRAM memory module specified to operate at 200 MHz using DDR-400 chips, 3.200 GByte/s bandwidth
Note: All RAM speeds in-between or above these listed specifications are not standardized by JEDEC — most often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.
The package sizes in which DDR SDRAM is manufactured are also standardised by JEDEC.
There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the speed that the chip is guaranteed to run at. Hence you can run DDR SDRAM at lower clock speeds than it was made for (underclocking) or higher clock speeds than it was made for (overclocking).
DDR SDRAM DIMMs have 184 pins (as opposed to 168 pins on SDR SDRAM, or, 240 pins on DDR-2), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDR SDRAM has two). DDR operates at a voltage of 2.5 V, compared to 3.3 V for SDR SDRAM. This can significantly reduce power usage.
Many new chipsets use these memory types in dual-channel or even quad channel configurations, which doubles or quadruples the effective bandwidth.
[edit] Module characteristics
- Size.
- # of DRAM Devices. Number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy both sides of module, or just single side. Corresponding modules are called Dual Sided and Single Sided. The maximum amount of chips per DDR module is 36 (9x4).
- # of DRAM rows (ranks). Any given module can have 1, 2 or 4 rows, but only 1 row of a module can be active at any moment of time. When module has 2 or more rows, memory controller must periodically switch them by performing close and open operations.
- Timings: CAS Latency (CL), Clock Cycle Time (tCK), Row Cycle Time (tRC), Refresh Row Cycle Time (tRFC), Row Active Time (tRAS).
Module and chip characteristics are inherently linked.
Total module size is a product of one chip size by number of chips. ECC modules multiply it by 8/9 because they use one bit per every byte for error correction. A module of any particular size can therefore be assembled either from 36 small chips, or 18 or 9 bigger ones.
DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using x8 chips instead of x4 will have more ranks.
| Module size | Number of chips | Chip size | Chip organization | Number of rows (ranks) |
|---|---|---|---|---|
| 1 GB | 36 | 256 Mbit | 64M x 4 | 2 |
| 1 GB | 18 | 512 Mbit | 64M x 8 | 2 |
| 1 GB | 18 | 512 Mbit | 128M x 4 | 1 |
This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory module, because all these variations can be sold under one price position without stating whether they are x4 or x8, single or dual ranked.
There is a common belief that number of module rows or ranks equals number of sides. As above data shows, this is not true. One can find (2-side, 1-rank) or (2-side, 4-rank) modules. One can even think of 1-side, 2-rank memory module having 16(18) chips on single side x8 each, but it's unlikely such a module was ever produced.
[edit] Alternatives
DDR (DDR1) is now being superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR-DRAM. DDR2 has become the standard, since QDR (Quad Data Rate) is too complex to affordably implement, while XDR is lacking support.
DDR Prefetch buffer width is 2 bits, DDR2 uses 4 bits. Although the effective clock speeds of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.[1]
Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher.
RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets.
[edit] MDDR
MDDR is an acronym that some enterprises use for Mobile DDR_SDRAM, a type of memory used in some portable electronic devices, like cell phones, handhelds, and digital audio players. While standard DDR SDRAM operates at a voltage of 2.5V, MDDR operates at voltage of 1.8V, which allows a reduced power consumption.
