Cyrix coma bug

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The Cyrix coma bug is a design flaw in Cyrix 6x86, 6x86L, and early 6x86MX processors that allows a non-privileged program to completely lock the computer.

1 Discovery
2 Analysis
3 Workarounds
4 See also
5 Notes
6 External links

[edit] Discovery

According to Andrew Balsa, around the time of the discovery of the f00f bug on Intel Pentium, Serguei Shtyliov of Moscow found a flaw in a Cyrix processor while developing an IDE disk driver in assembly language. Alexandr Konosevich, from Omsk, further researched the bug, and coauthored an article with Uwe Post in the German technology magazine, C't, calling it the "hidden CLI bug" (CLI is the instruction which disables interrupts on the Cyrix). Balsa, as a member on the Linux-kernel mailing list, confirmed that the following program could be compiled and run by an unprivileged user:

static unsigned char c[4] = {0x36, 0x78, 0x38, 0x36};
main()
{
 asm ("movl $c, %ebx\n\t"
 "again: xchgl (%ebx), %eax\n\t"
 "movl %eax, %edx\n\t"
 "jmp again\n\t");
}

Execution of this program renders the processor completely useless, as it enters an infinite loop that cannot be interrupted. This presents a security flaw because any user with access to a Cyrix system with this bug could prevent other users from using the system. Exploitation of this flaw would therefore be a denial-of-service attack. It is similar to execution of a Halt and Catch Fire instruction, although the coma bug is not any one particular instruction.

[edit] Analysis

What causes the bug is not an interrupt mask, nor are interrupts being explicitly disabled. Instead, an anomaly in the Cyrix's instruction pipeline prevents interrupts from being serviced for the duration of the loop; since the loop never ends, interrupts will never be serviced. The xchg^[1] instruction is atomic, meaning that other instructions are not allowed to change the state of the system while it is executed. In order to ensure this atomicity, the designers at Cyrix made the xchg uninterruptible. However, because of pipelining and branch predicting, another xchg enters the pipeline before the previous one completes, leaving the processor in this uninterruptible state forever.

[edit] Workarounds

The first way to prevent this bug is to enable bit 0x10 in the configuration register CCR1. Alternatively, Cyrix provided an undocumented way to fix this, by serializing the xchg opcode, thus bypassing the pipeline.