Cray-3

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The Cray-3 was intended to be Cray Research's successor to the Cray-2 supercomputer. The system was to be the first major application of gallium arsenide (GaAs) semiconductors in computing. The project was not considered a success, and only one Cray-3 was delivered. Seymour Cray moved onto the Cray-4 design, but was killed in a car accident before it was fully assembled.

Work on the design started in the late 1980s at Cray's new lab in Colorado Springs, CO, where he had moved in order to avoid managerial oversight from Cray headquarters in Chippewa Falls, WI. This lab should not be confused with a prior attempt to start Cray Laboratories in Boulder, CO for the earlier Cray 2. Cray had always attacked the problem of increased speed with three simultaneous advances: more functional units to give the system higher parallelism, tighter packaging to decrease signal delays, and faster components to allow for a higher clock speed. The Cray-2 had introduced a novel 3D-packaging system for its integrated circuits to allow higher densities, and it appeared that there was some room for improvement in this process. But for the sort of 10x performance increases Cray demanded, packaging alone would not be enough.

The Cray-2 appeared to be pushing the limits of speed of silicon-based transistors at 4.1 ns (244 MHz), and it didn't appear that anything more than another 2x would be possible. Cray had intended to use gallium arsenide circuitry in the Cray-2, which would not only offer much higher switching speeds, but also used less energy and thus ran cooler as well. At the time, the state of GaAs manufacturing simply wasn't up to the task of supplying a supercomputer, however, but by the mid-1980s things had changed and Cray decided it was the only way forward. In the end he decided the only solution was to invest in a GaAs chipmaking startup, GigaBit Logic, and use them as their internal supplier.

This was an extremely risky move -- if the technology didn't pan out the project was doomed to fail. The Cray-2 had not been terribly successful, and since the company was also in the midst of developing the Cray Y-MP, management eventually decided that the Cray-3 should be put on "low priority" development. This was not the first time this had happened to Cray, and as in the past he decided to form his own company. The result was Cray Computer Corporation supported to a large degree by his major customer, NCAR.

Typical module layout, with a 4x4 arrangement of "submodules", stacked 4-deep. The metal connectors on the bottom are power connections. Courtesy Alan Kilian
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Typical module layout, with a 4x4 arrangement of "submodules", stacked 4-deep. The metal connectors on the bottom are power connections. Courtesy Alan Kilian

As with previous designs, the core of the Cray-3 consisted of a number of "modules", each containing several circuit boards packed with parts. In order to increase density, the individual GaAs chips were not "packaged", and instead several were mounted directly with ultrasonic gold bonding to a 4"x4" board. The boards were then turned over and mated to a second board carrying the electrical wiring, with wires on this card running through holes to the "bottom" (opposite the chips) side of the chip carrier where they were bonded. The result was a single 4x4 card with the chips sandwitched in the middle of two thin boards. These "submodules" were then stacked 4-deep, and as in the Cray-2, wired to each other to make a 3D circuit. Unlike the Cray-2, the Cray-3 modules also included edge connectors along the sides, and 16 such submodules were connected together to make a single 16"x16"x.75" module. Even with this advanced packaging the circuit density was low even by 1990s standards, at about 100 gates per cubic inch. Modern CPUs offer gate counts of millions per square inch, and the move to 3D circuits is still just being considered.

Thirty-two such modules were then stacked and wired together with a mass of twisted-pair wires into a single processor. The modules were held together in an aluminum chassis known as a "brick". The bricks were immersed in liquid fluorinert for cooling, as in the Cray-2. A four-processor system dissipated about 88 kW of power. The entire four-processor system was about 20" tall and front-to-back, and a little over two feet wide. The processors sat at the top of a 3x3x4 cabinet, with the memory below it, and then the power supplies and cooling systems on the bottom. All in all the Cray-3 was considerably smaller than the Cray-2, itself considered tiny.

Complete processor "brick". The modules are visible inside, mounted vertically. Courtesy Alan Kilian
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Complete processor "brick". The modules are visible inside, mounted vertically. Courtesy Alan Kilian

The basic cycle time was 2.11 ns, or 474 MHz, allowing each processor to reach about 0.948 GFLOPs, and the machine as a whole 15.17 GFLOP. Key to the high performance was the high-speed access to main memory, which allowed each process to burst up to 8 GB/s.

Development dragged on, and serial number 1 was not delivered to NCAR until May 1993. Although the original design called for machines with 1 to 16 processors, NCAR's model included 4 and included a 128-MWord (64-bit words, 6GB) main memory. In production it was learned that the square root code contained a bug, and one of their four CPU's was not running reliably. Replacements to fix both problems were provided, but apparently not delivered. NCAR had not yet paid for the machine, and CCC folded in 1995 after burning through about 300 million dollars of financing. NCAR's machine was officially decommissioned the next day, but in fact two of the processors were removed, and the machine was used unofficially for some time after that.

Seven "tanks" were built for Cray-3 machines (most for smaller two-CPU machines), but NCAR's was the only one ever delivered. Three of the smaller tanks were used on the Cray-4 project, essentially a Cray-3 with 64 faster CPUs running at 1 ns (1 GHz). Another was used for the Cray-3/SSS project.

The failure of the Cray-3 seems to have little to do with the machine itself, however, and everything to do with the changing political climate. The machine was being designed during the collapse of the Warsaw Pact and ending of the cold war, which led to a massive downsizing in "large machine" supercomputer purchases. The market has since picked up, but only for massively parallel machines, and it appears the days of the single-processor design are over. The entire gallium arsenide market was likewise afflicted, with both the chip making and analog amplifier uses being hard hit. It is still believed that if not for the end of the cold war, many more machines would be using GaAs today.

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