AMD K8L

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Current event marker This article contains information about a scheduled or expected future product.
It may contain preliminary or speculative information, and may not reflect the final version of the product.

The AMD K8L is the immediate successor to the AMD K8 series of processors (i.e. Athlon 64, Opteron, Sempron 64, and sharing technologies with the Socket S1 Turion 64s). Little is known about it yet as it has not been officially announced. However, its existence is confirmed by Henri Richard, AMD executive vice president and chief officer for marketing and sales in an interview dated 14 March 2006 by DigiTimes.

K8L comes after the Revision G of the AMD64 microprocessors. The name K8L avoids poor marketing using the name K9.[citation needed]

Floor plan of the Deerhound die
Enlarge
Floor plan of the Deerhound die

Contents

[edit] Schedule of launch and delivery

[edit] Official timeline

On July 21, 2006, AMD President and COO Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of K8L (Revision H) microprocessors is slated for mid-2007; and that it will contain a quad core version for servers, workstations, and high-end desktops, as well as a dual core version for consumer Desktops. AMD will perform a live demonstration of K8L microprocessors before the end of 2006. Some of the Revision H Opterons shipped in 2007 will be at Thermal Design Power of 68W.

On August 15, 2006, at the launch of the first Socket F(1207) dual core Opterons, AMD announced that the firm has reached the final design stage (i.e. Tape-out) of K8L quad-core Opterons, codenamed Deerhound. This will now go to the test and validation stage; and will be available for samples in the next several months.[1]

As of October 2006, reports have been naming the desktop part codenamed Altair, and the core speeds of the parts range from 2.4GHz - 2.9GHz respectively, 512KB L2 cache each core, 2MB L3 cache, using HyperTransport 3.0, with a TDP of 125W.[2] In recent reports, K8L also comes in single core (codenamed Spica) and dual core with or without L3 cache (codenamed Antares and Arcturus respectively) variants under the same microarchitecture. [3]

[edit] Live demonstrations

On November 30, 2006, AMD live demoed the native quad core chip known as "Barcelona" for the first time in public,[4] while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than Intel Xeon 5355 Clovertown.[5] There has been some more details of this first revision of the next generation AMD microprocessor design surfacing on the web recently, with clock speeds.[6][7]

[edit] Sister microarchitecture

Also due in a similar timeframe will be a sister microarchitecture to K8L, which will focus on lower power consumption chips in mobile platforms as well as innovative small form factor solutions. This microarchitecture will contain specialized features such as separate power planes for cores and other on die components; mobile optimized crossbar switch and memory controller; link power management for HyperTransport 3.0; and others. At this time, AMD has simply dubbed it "New Mobile Core", without giving a specific codename. This will represent a change in design philosophy from a singular x86 microarchitecture covering from servers through laptops, to a dual design focus model, which will provide better opportunity for diversification at the platform level.

On the December 2006 analyst day, Executive VP Marty Seyer announced the new mobile core code-named "Griffin" to be launched in 2008. [8]

[edit] Iterations of K8L release

In late 2007 to Q2 2008, there will be a modification to the K8L core to be fabricated at 45 nm node,[9] with enhancements such as FB-DIMM support, Direct Connect Architecture 2.0, enhanced RAS, and probably more for the processor die. The K8L platform will also add support for I/O Virtualization, PCI Express 2.0, 10 Gigabit NIC, and more.

However, reports have suggested that FB-DIMM support has been dropped from future roadmaps of the majority of AMD products since popularity is low.[10][11] Also, FB-DIMM's future as an industry standard has been called into question.

A recent article published by The Inquirer, corroborates the earlier reports of the timeline (as cited in this article). According to this report, there will be three iterations of the K8L core: one named Barcelona, due in Q2 of 2007, with new CPU core components and microarchitecture, but built on the old HyperTransport 2.0 infrastructure; the second is Budapest for single socket systems (single sockets are AM2/AM3), with HyperTransport 3.0; and the third is an update of the server chip, probably also with HyperTransport 3.0 and DDR3 implementation, due in Q1-Q2 2008.[12]

[edit] Probable K8L features

[edit] Fabrication technology

Possible die size of quad-core K8
Enlarge
Possible die size of quad-core K8

AMD will most likely introduce K8L microprocessors manufactured at 65 nm feature width using Silicon-on-insulator (SOI) technology, since the release of K8L coincides with the volume ramp of this manufacturing process.[13] The servers will be produced for Socket F (1207) infrastructure, the only server socket on AMD's near-term roadmap; the desktop parts will come on Socket AM2, in the form of dual-core and single-core chips code-named Brisbane and Sparta respectively. Rumors run of a new socket, Socket AM3, having the same number of contacts, that will replace Socket AM2.

AMD has announced in its Technology Analyst Day 2006, that the use of CTT and STI will finally lead to the implementation of Silicon-Germanium-on-Insulator (SGOI) on 65 nm process CPUs. [citation needed]

[edit] Supported DRAM standards

Given the state of current DDR2 RAM, it is possible that K8L will introduce technologies that hide the additional latency penalty DDR2 imposes over DDR; for example, additional caches. The K8 is particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an CPU-integrated memory controller; increased latency in the external modules negates the usefulness of this feature. DDR2 introduces some additional latency over traditional DDR since the DRAM is internally driven by a clock at one quarter of the external data frequency, as opposed to one half for DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on CAS Latency alone are not sufficient. For example, the upcoming K8 for AM2 is known to demonstrate similar performance using DDR2-533 memory as current DDR-based versions achieve with DDR-400, although the new processor and platform can achieve gains with DDR2-800 and above. Currently the K8 Socket AM2 chips support DDR2-800, with improved DDR2 memory following upgrade trends across the new/current generation.

[edit] Higher computational throughput

It was also reported by certain sources (such as The Inquirer and Geek.com) that K8L will likely feature a doubling in the number and/or width of floating point units in the cores. With the help of the doubled instruction fetch and load, AMD K8L is expected to increase the suitability of the processor to scientific and high-performance computing tasks and potentially improve its level of competition with Intel's Itanium 2, Core 2 Duo and other processors in the markets.

Many of the other improvements in computational throughput of each K8L core are listed in the section below; although the timeline for introduction of many of these new technologies are uncertain, due to the introduction of different revisions of K8L at different times, as scheduled by AMD, as well as microarchitectures beyond K8L, one dubbed preliminarily as AMD Fusion; as an extension of both the Torrenza initiative, with a much closer than a platform level integration.[14][15]

[edit] Features for future AMD microarchitectures

These may be present in the original K8L processors or a more future AMD64 chip, by various reports in the time frame of Q1 07, Q2 07, Q3 07, or for chips using newer sockets such as Socket AM3, Q1 08; (this variation in reports is probably due to reportings about the same microarchitecture core on different platforms, with each source of these reports only given incomplete information); and further microarchitectures in 2009 and beyond.

  • ISA additions and extensions:
    • New instructions LZCNT, POPCNT, EXTRQ/INSERTQ, MOVNTSD/MOVNTSS
    • Extension to the AMD64 instruction set during 2007; it is unclear whether AMD plans this for Revision G or Revision H chips.
    • New SIMD instruction set and new, wide SIMD units; in a yet unspecified time frame.
    • Implementation and possibly adding extensions of SSSE3 (which was called "SSE4" prior to its official name announced) and/or SSE4 , which AMD codenamed SSE4a.
  • Integration of new technologies onto CPU die:
    • Four processor cores (Quad-core)
    • independently changeable core voltages
    • Split Power Planes, first dubbed Dynamic Independent Core Engagement or D.I.C.E. by AMD and is now known as Enhanced Cool 'n' Quiet, which "clock-gen" or PLL (Phase-locked loop) present in each core and the northbridge, allowing the cores and the northbridge to scale up and down power consumptions automatically. [16]
    • Large Level-3 non-inclusive cache, initially expected to be a minimum of 2MB shared cache between processing cores on a single die (each with 512 KB of independent second-level cache).
    • Z-RAM technology, projected to bring 4-5 times the cell density of current SRAM for CPU cache, which may or may not be in time for 2007 implementation.
  • Improvements in the memory subsystem:
    • 48-bit memory addressing for the address BUS of massive memory subsystems
    • Simultaneous DDR2, DDR3 support
    • FB-DIMM support in server processors for Opterons after year 2008
    • Memory mirroring support and Enhanced RAS
    • Possible use of an interim socket dubbed "Socket AM2+" which only supports HT 3.0 and DDR2.
    • Possible use of new socket (Socket AM3), containing both DDR2 and DDR3 controllers: AM3 chips to be backward compatible with Socket AM2 motherboards; but socket AM2 chips will not be compatible with AM3 motherboards. Recent information indicates that Socket AM3 may not be deployed until AMD's 45nm manufacturing process is ready, due to the anticipated slow adoption of DDR3 (despite both bandwidth and energy efficiency over DDR2); [17].
    • In recent reports[18], AMD K8L CPUs will adapt two sockets namely "Socket AM2+" and "Socket F+", which is capable of running HyperTransport 3.0 with the use of DDR2 DIMMs. The "Socket AM3" will be postponed until 2008, the two suggested sockets have the same pin definitions as the old Socket AM2 and Socket F with the only difference of the capability of running HyperTransport 3.0 at working frequencies higher than 1.6 GHz.
    • Quad-core parts are rumored to have two 64-bit independent memory controllers each with its own physical address space thus giving an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environment. This approach is in a contrary to the previous "interleaved" design, where the two 64-bit data channels are bounded to a single common address space. It will be the first single-chip implementation of the non-uniform memory access architecture.
  • Improvements in system interconnect:
    • HyperTransport retry support
    • Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
    • Support for HyperTransport 4.0 at an unspecified date; according to techreport.com[19] and some other sources.
    • Increased number of HyperTransport links per processor package to 4 (from 3 in current Opterons), and maximum socket count to 32; this will be implemented in Revision H Opterons.
  • Platform-level enhancements with additional functionality:
    • Official support for coprocessors connected via HyperTransport Expansion Slot (HTX)
    • Opening cache coherent HyperTransport (ccHT) standard to third party developments: Torrenza initiative.
    • Vector coprocessor support, which will bring 1-2 orders of FP/SIMD performance increase if a specialized processor is attached via coherent HyperTransport link in a specialized socket.
    • Possible integration of GPU functionalities onto a CPU die or package.

[edit] Media discussions

Note: These media discussions are sorted by dates of publishing in ascending orders.

[edit] References

  1. ^ "Next-Generation AMD Opteron Paves The Way For Quad-Core", crn.com, 15 Aug 2006.
  2. ^ "AMD Quad-Core Altair upcoming in 2007 Q3", HKEPC, 3 Oct 2006.
  3. ^ "AMD to enter K8L era in 2H 2007", HKEPC, 4 Oct 2006.
  4. ^ "AMD Demonstrates Its Quad Core Server Chips", CNET.com, 30 Nov 2006.
  5. ^ "AMD Demonstrates Barcelona; The First True, Native Quad Core Opteron", legitreviews.com, 30 Nov 2006.
  6. ^ "Quick Look at AMD Quad Core Barcelona", arstechnica.com.
  7. ^ The Inquirer article
  8. ^ "AMD updates Opteron, Turion roadmaps", informationweek.com, 14 Dec 2006.
  9. ^ "AMD Outlines Quad Core Computing", www.pcpro.co.uk, 19 Sept 2006.
  10. ^ "Intel Pulls Back from FB-DIMM", inquirer.net, 7 Sept 2006.
  11. ^ "No Shocker Here", legitreviews.com, 15 Sept 2006.
  12. ^ "AMD Quad Cores: The Whole Story Unfolded", inquirer.net, 16 Sep 2006.
  13. ^ "An AMD Update: Fab 36 Begins Shipments, Planning for 65nm and AM2 Performance", AnandTech, April 4, 2006.
  14. ^ "AMD's "Fusion" Processor to Merge CPU and GPU", tomshardware.com, 25 Oct 2006.
  15. ^ "AMD Announces "Fusion" CPU/GPU Program", dailytech.com, 25 Oct 2006.
  16. ^ "AMD Next Generation Processor Technology Slides", HardOCP, 22 Aug 2006.
  17. ^ "AMD to postpone DDR3 adoption, first quad-core K8L resident Socket AM2+", digitimes.com, 3 Oct 2006.
  18. ^ "AMD Quad-Core Altair upcoming in 2007 Q3", HKEPC, 3 Oct 2006.
  19. ^ "AMD outlines future technology directions", TechReport, 17 Oct 2005.

[edit] External links


v • d • e
List of AMD microprocessors • AMD • List of AMD CPU slots, sockets
Discontinued: Am2900 • Am29000 • Am9080 • Am286 • Am386 • Am486 • Am5x86 • K5 • K6 • K6-2 • K6-III • Duron • Athlon
Current Production: Sempron • Athlon 64 • Athlon 64 X2 • Turion 64 • Turion 64 X2 • Opteron
Upcoming: K8L • Fusion
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