65 nanometer

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CMOS manufacturing
processes

1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 65 nanometer (65 nm) process is (as of 2006) the most advanced lithographic node for volume semiconductor manufacturing; however, it will soon be eclipsed when 45 nanometer lithography becomes commercially viable. Minimum feature sizes can reach as low as 35 nm on a "65 nm" process. For reference, the Human Immunodeficiency Virus (HIV) is around 120 nm in diameter, a human red blood cell typically 6000-8000 nm in diameter, and a human hair typically 80000 nm in diameter. Companies currently planning 65 nm production ramps include AMD, IBM, Texas Instruments, Cypress Semiconductor and TSMC. Intel is doing 65 nm. Samsung is already deploying 50 nm process technology for NAND flash memory.

While average feature sizes are 65 nm, the wavelength of light used is actually 193 nm and 248 nm. A variety of techniques, such as phase-shifting masks, are used to make sub-wavelength features.

As feature sizes shrink, devices are subject to a potentially detrimental phenomenon called leakage. Transistor leakage can be primarily addressed through raising threshold voltage, substrate bias and high-k gate dielectrics. As these methods can compromise performance, straining the silicon channel has been applied to compensate.

Intel's Prescott core on its original 90 nm process was widely criticized at launch due to high leakage (and therefore heat output and power consumption).

Interestingly enough, IEDM papers from Intel in 2002, 2004 and 2005 indicate that the minimum feature pitch did not change much (220 nm to 210 nm) going from 90 nm to 65 nm node, even for the low power process. This suggests that scaling down the distance between microprocessor transistors is slowing down dramatically, but chip size can be made smaller by crowding a larger fraction of transistors at the minimum distance.